// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  smf0_harden_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2018/9/28
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2020/12/25 10:33:43 Create file
// ******************************************************************************

#ifndef SMF0_HARDEN_C_UNION_DEFINE_H
#define SMF0_HARDEN_C_UNION_DEFINE_H

/* Define the union csr_crg_cfg_smf0_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_ring_smf0_harden : 1;          /* [0] */
        u32 icg_en_smf_smf0_harden : 1;           /* [1] */
        u32 icg_en_smf_div2_smf0_harden : 1;      /* [2] */
        u32 icg_en_virtio_core_smf0_harden : 1;   /* [3] */
        u32 icg_en_smeg_smf0_harden : 1;          /* [4] */
        u32 srst_req_ring_smf0_harden : 1;        /* [5] */
        u32 srst_req_smf_smf0_harden : 1;         /* [6] */
        u32 srst_req_virtio_core_smf0_harden : 1; /* [7] */
        u32 srst_req_smf_div2_smf0_harden : 1;    /* [8] */
        u32 srst_req_smeg_smf0_harden : 1;        /* [9] */
        u32 rsv_1 : 22;                           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_smf0_harden_u;

/* Define the union csr_crg_cfg_smf1_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_ring_smf1_harden : 1;          /* [0] */
        u32 icg_en_smf_smf1_harden : 1;           /* [1] */
        u32 icg_en_smf_div2_smf1_harden : 1;      /* [2] */
        u32 icg_en_virtio_core_smf1_harden : 1;   /* [3] */
        u32 icg_en_smeg_smf1_harden : 1;          /* [4] */
        u32 srst_req_ring_smf1_harden : 1;        /* [5] */
        u32 srst_req_smf_smf1_harden : 1;         /* [6] */
        u32 srst_req_virtio_core_smf1_harden : 1; /* [7] */
        u32 srst_req_smf_div2_smf1_harden : 1;    /* [8] */
        u32 srst_req_smeg_smf1_harden : 1;        /* [9] */
        u32 rsv_3 : 22;                           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_smf1_harden_u;

/* Define the union csr_crg_cfg_stftile0_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_qcm_stftile0_harden : 1;       /* [0] */
        u32 icg_en_tile_stftile0_harden : 1;      /* [1] */
        u32 icg_en_tile_div2_stftile0_harden : 1; /* [2] */
        u32 icg_en_ring_stftile0_harden : 1;      /* [3] */
        u32 srst_req_cnb_stftile0_harden : 1;     /* [4] */
        u32 srst_req_l2i_stftile0_harden : 1;     /* [5] */
        u32 srst_req_mbist_stftile0_harden : 1;   /* [6] */
        u32 srst_req_mtc_stftile0_harden : 1;     /* [7] */
        u32 srst_req_qcm_stftile0_harden : 1;     /* [8] */
        u32 srst_req_rep_stftile0_harden : 1;     /* [9] */
        u32 srst_req_ring_stftile0_harden : 1;    /* [10] */
        u32 srst_req_tiu_stftile0_harden : 1;     /* [11] */
        u32 srst_req_tou_stftile0_harden : 1;     /* [12] */
        u32 tile_sys_clk_sel_stftile0_harden : 1; /* [13] */
        u32 rsv_5 : 18;                           /* [31:14] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_stftile0_harden_u;

/* Define the union csr_crg_cfg_stftile1_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_qcm_stftile1_harden : 1;       /* [0] */
        u32 icg_en_tile_stftile1_harden : 1;      /* [1] */
        u32 icg_en_tile_div2_stftile1_harden : 1; /* [2] */
        u32 icg_en_ring_stftile1_harden : 1;      /* [3] */
        u32 srst_req_cnb_stftile1_harden : 1;     /* [4] */
        u32 srst_req_l2i_stftile1_harden : 1;     /* [5] */
        u32 srst_req_mbist_stftile1_harden : 1;   /* [6] */
        u32 srst_req_mtc_stftile1_harden : 1;     /* [7] */
        u32 srst_req_qcm_stftile1_harden : 1;     /* [8] */
        u32 srst_req_rep_stftile1_harden : 1;     /* [9] */
        u32 srst_req_ring_stftile1_harden : 1;    /* [10] */
        u32 srst_req_tiu_stftile1_harden : 1;     /* [11] */
        u32 srst_req_tou_stftile1_harden : 1;     /* [12] */
        u32 tile_sys_clk_sel_stftile1_harden : 1; /* [13] */
        u32 rsv_7 : 18;                           /* [31:14] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_stftile1_harden_u;

/* Define the union csr_crg_cfg_ipsurx_petx_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_ring_ipsurx_petx_harden : 1;         /* [0] */
        u32 icg_en_dp_network_ipsurx_petx_harden : 1;   /* [1] */
        u32 srst_req_ring_ipsurx_petx_harden : 1;       /* [2] */
        u32 srst_req_dp_network_ipsurx_petx_harden : 1; /* [3] */
        u32 rsv_9 : 28;                                 /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_ipsurx_petx_harden_u;

/* Define the union csr_crg_cfg_ts_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_ring_ts_harden : 1;      /* [0] */
        u32 icg_en_ts_ts_harden : 1;        /* [1] */
        u32 icg_en_cnb2apb_ts_harden : 1;   /* [2] */
        u32 srst_req_ring_ts_harden : 1;    /* [3] */
        u32 srst_req_ts_ts_harden : 1;      /* [4] */
        u32 srst_req_cnb2apb_ts_harden : 1; /* [5] */
        u32 rsv_11 : 26;                    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_ts_harden_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_apb_chain_mag_fc_sds_harden : 1;         /* [0] */
        u32 icg_en_mag_mag_fc_sds_harden : 1;               /* [1] */
        u32 icg_en_mac_core_mag_fc_sds_harden : 1;          /* [2] */
        u32 icg_en_mac_ptp_mag_fc_sds_harden : 1;           /* [3] */
        u32 icg_en_an_lt_cfg_mag_fc_sds_harden : 1;         /* [4] */
        u32 icg_en_led_mag_fc_sds_harden : 1;               /* [5] */
        u32 icg_en_serdes6_mag_rx_su_mag_fc_sds_harden : 1; /* [6] */
        u32 icg_en_serdes7_mag_rx_su_mag_fc_sds_harden : 1; /* [7] */
        u32 icg_en_an_core_mag_fc_sds_harden : 8;           /* [15:8] */
        u32 icg_en_serdes6_mclk_mag_fc_sds_harden : 1;      /* [16] */
        u32 icg_en_serdes7_mclk_mag_fc_sds_harden : 1;      /* [17] */
        u32 icg_en_fc_apb_mag_fc_sds_harden : 1;            /* [18] */
        u32 icg_en_dp_com_mag_fc_sds_harden : 1;            /* [19] */
        u32 icg_en_p01_rx_pma_mag_fc_sds_harden : 1;        /* [20] */
        u32 icg_en_p23_rx_pma_mag_fc_sds_harden : 1;        /* [21] */
        u32 rsv_13 : 10;                                    /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_0_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_apb_chain_mag_fc_sds_harden : 1;  /* [0] */
        u32 srst_req_mag_mag_fc_sds_harden : 1;        /* [1] */
        u32 srst_req_mac_core_mag_fc_sds_harden : 1;   /* [2] */
        u32 srst_req_mac_t_mag_fc_sds_harden : 1;      /* [3] */
        u32 srst_req_mac_ptp_mag_fc_sds_harden : 1;    /* [4] */
        u32 srst_req_an_lt_cfg_mag_fc_sds_harden : 1;  /* [5] */
        u32 srst_req_led_mag_fc_sds_harden : 1;        /* [6] */
        u32 srst_req_mac_logic_mag_fc_sds_harden : 1;  /* [7] */
        u32 srst_req_an_core_mag_fc_sds_harden : 8;    /* [15:8] */
        u32 srst_req_fc_apb_mag_fc_sds_harden : 1;     /* [16] */
        u32 srst_req_dp_com_mag_fc_sds_harden : 1;     /* [17] */
        u32 srst_req_p01_rx_pma_mag_fc_sds_harden : 1; /* [18] */
        u32 srst_req_p23_rx_pma_mag_fc_sds_harden : 1; /* [19] */
        u32 rsv_15 : 12;                               /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_1_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_serdes6_txo_mag_fc_sds_harden : 4;    /* [3:0] */
        u32 icg_en_serdes7_txo_mag_fc_sds_harden : 4;    /* [7:4] */
        u32 icg_en_serdes6_rxo_mag_fc_sds_harden : 4;    /* [11:8] */
        u32 icg_en_serdes7_rxo_mag_fc_sds_harden : 4;    /* [15:12] */
        u32 icg_en_serdes6_pma_tx_mag_fc_sds_harden : 4; /* [19:16] */
        u32 icg_en_serdes7_pma_tx_mag_fc_sds_harden : 4; /* [23:20] */
        u32 icg_en_serdes6_pma_rx_mag_fc_sds_harden : 4; /* [27:24] */
        u32 icg_en_serdes7_pma_rx_mag_fc_sds_harden : 4; /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_2_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_serdes6_spi_mag_fc_sds_harden : 4;    /* [3:0] */
        u32 icg_en_serdes7_spi_mag_fc_sds_harden : 4;    /* [7:4] */
        u32 icg_en_lt_spi_mag_fc_sds_harden : 8;         /* [15:8] */
        u32 icg_en_serdes6_mac_rx_mag_fc_sds_harden : 8; /* [23:16] */
        u32 icg_en_serdes7_mac_rx_mag_fc_sds_harden : 4; /* [27:24] */
        u32 rsv_17 : 4;                                  /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_3_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_serdes6_an_rx_mag_fc_sds_harden : 4;  /* [3:0] */
        u32 icg_en_serdes7_an_rx_mag_fc_sds_harden : 4;  /* [7:4] */
        u32 icg_en_serdes6_lt_rx_mag_fc_sds_harden : 4;  /* [11:8] */
        u32 icg_en_serdes7_lt_rx_mag_fc_sds_harden : 4;  /* [15:12] */
        u32 icg_en_serdes6_mac_tx_mag_fc_sds_harden : 4; /* [19:16] */
        u32 icg_en_serdes7_mac_tx_mag_fc_sds_harden : 4; /* [23:20] */
        u32 icg_en_serdes6_an_tx_mag_fc_sds_harden : 4;  /* [27:24] */
        u32 icg_en_serdes7_an_tx_mag_fc_sds_harden : 4;  /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_4_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_serdes6_lt_tx_mag_fc_sds_harden : 4; /* [3:0] */
        u32 icg_en_serdes7_lt_tx_mag_fc_sds_harden : 4; /* [7:4] */
        u32 icg_en_serdes6_rxaux_mag_fc_sds_harden : 2; /* [9:8] */
        u32 icg_en_serdes7_rxaux_mag_fc_sds_harden : 2; /* [11:10] */
        u32 rsv_19 : 20;                                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_5_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_6_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_serdes6_pma_tx_mag_fc_sds_harden : 4; /* [3:0] */
        u32 srst_req_serdes7_pma_tx_mag_fc_sds_harden : 4; /* [7:4] */
        u32 srst_req_serdes6_pma_rx_mag_fc_sds_harden : 4; /* [11:8] */
        u32 srst_req_serdes7_pma_rx_mag_fc_sds_harden : 4; /* [15:12] */
        u32 srst_req_serdes6_spi_mag_fc_sds_harden : 4;    /* [19:16] */
        u32 srst_req_serdes7_spi_mag_fc_sds_harden : 4;    /* [23:20] */
        u32 srst_req_lt_spi_mag_fc_sds_harden : 8;         /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_6_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_7_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_serdes6_mac_rx_mag_fc_sds_harden : 4; /* [3:0] */
        u32 srst_req_serdes7_mac_rx_mag_fc_sds_harden : 4; /* [7:4] */
        u32 srst_req_serdes6_an_rx_mag_fc_sds_harden : 4;  /* [11:8] */
        u32 srst_req_serdes7_an_rx_mag_fc_sds_harden : 4;  /* [15:12] */
        u32 srst_req_serdes6_lt_rx_mag_fc_sds_harden : 4;  /* [19:16] */
        u32 srst_req_serdes7_lt_rx_mag_fc_sds_harden : 4;  /* [23:20] */
        u32 srst_req_serdes6_mac_tx_mag_fc_sds_harden : 4; /* [27:24] */
        u32 srst_req_serdes7_mac_tx_mag_fc_sds_harden : 4; /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_7_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_8_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_serdes6_an_tx_mag_fc_sds_harden : 4; /* [3:0] */
        u32 srst_req_serdes7_an_tx_mag_fc_sds_harden : 4; /* [7:4] */
        u32 srst_req_serdes6_lt_tx_mag_fc_sds_harden : 4; /* [11:8] */
        u32 srst_req_serdes7_lt_tx_mag_fc_sds_harden : 4; /* [15:12] */
        u32 srst_req_an_rs_mag_fc_sds_harden : 8;         /* [23:16] */
        u32 srst_req_lt_rs_mag_fc_sds_harden : 8;         /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_8_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_9_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_phy_rx_logic_mag_fc_sds_harden : 8;  /* [7:0] */
        u32 srst_req_port_rx_logic_mag_fc_sds_harden : 8; /* [15:8] */
        u32 srst_req_phy_tx_logic_mag_fc_sds_harden : 8;  /* [23:16] */
        u32 srst_req_port_tx_logic_mag_fc_sds_harden : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_9_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_10_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 func_mbist_clk_sel_mag_fc_sds_harden : 1;        /* [0] */
        u32 serdes6_pma_rx_su_clk_sel_mag_fc_sds_harden : 1; /* [1] */
        u32 serdes7_pma_rx_su_clk_sel_mag_fc_sds_harden : 1; /* [2] */
        u32 p01_pma_rx_clk_sel_mag_fc_sds_harden : 1;        /* [3] */
        u32 p23_pma_rx_clk_sel_mag_fc_sds_harden : 1;        /* [4] */
        u32 rsv_21 : 27;                                     /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_10_u;

/* Define the union csr_crg_cfg_mag_fc_sds_harden_11_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_24 : 12;                                  /* [11:0] */
        u32 probe_sds_mag_sel_mag_fc_sds_harden : 1;      /* [12] */
        u32 icg_en_probe_mag_fc_sds_harden : 1;           /* [13] */
        u32 probe_mode_mag_fc_sds_harden : 1;             /* [14] */
        u32 sds_fc_mclk_icg_en_sel_mag_fc_sds_harden : 2; /* [16:15] */
        u32 mag_fc_hclk_clk_sel_mag_fc_sds_harden : 1;    /* [17] */
        u32 rsv_25 : 14;                                  /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_crg_cfg_mag_fc_sds_harden_11_u;

/* Define the union csr_icg_en_mag_fc_sds_harden_p0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_fc_ua_p0_mag_fc_sds_harden : 1;          /* [0] */
        u32 icg_en_dp_p0_mag_fc_sds_harden : 1;             /* [1] */
        u32 icg_en_tts_pma_tx_p0_mag_fc_sds_harden : 1;     /* [2] */
        u32 icg_en_fc_h_64b_tx_p0_mag_fc_sds_harden : 1;    /* [3] */
        u32 icg_en_fc_l_8g_tx_p0_mag_fc_sds_harden : 1;     /* [4] */
        u32 icg_en_fc_l_16g_tx_p0_mag_fc_sds_harden : 1;    /* [5] */
        u32 icg_en_tts_tx_p0_mag_fc_sds_harden : 1;         /* [6] */
        u32 icg_en_fc_h_tx_p0_mag_fc_sds_harden : 1;        /* [7] */
        u32 icg_en_endec_tx_p0_mag_fc_sds_harden : 1;       /* [8] */
        u32 icg_en_tts_pma_rx_p0_mag_fc_sds_harden : 1;     /* [9] */
        u32 icg_en_fc_h_64b_rx_p0_mag_fc_sds_harden : 1;    /* [10] */
        u32 icg_en_fc_l_8g_rx_p0_mag_fc_sds_harden : 1;     /* [11] */
        u32 icg_en_fc_l_16g_rx_p0_mag_fc_sds_harden : 1;    /* [12] */
        u32 icg_en_tts_rx_p0_mag_fc_sds_harden : 1;         /* [13] */
        u32 icg_en_fc_h_rx_p0_mag_fc_sds_harden : 1;        /* [14] */
        u32 icg_en_endec_rx_p0_mag_fc_sds_harden : 1;       /* [15] */
        u32 icg_en_lpsm_p0_mag_fc_sds_harden : 1;           /* [16] */
        u32 icg_en_bm8g_p0_mag_fc_sds_harden : 1;           /* [17] */
        u32 icg_en_psm_p0_mag_fc_sds_harden : 1;            /* [18] */
        u32 icg_en_bm_p0_mag_fc_sds_harden : 1;             /* [19] */
        u32 fc_p0_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */
        u32 fc_p0_mclk_sel_mag_fc_sds_harden : 1;           /* [21] */
        u32 fc_p0_bufman_p2p_mode_mag_fc_sds_harden : 1;    /* [22] */
        u32 fc_p0_mode_mag_fc_sds_harden : 3;               /* [25:23] */
        u32 rsv_27 : 6;                                     /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_icg_en_mag_fc_sds_harden_p0_u;

/* Define the union csr_srst_req_mag_fc_sds_harden_p0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_fc_ua_p0_mag_fc_sds_harden : 1;       /* [0] */
        u32 srst_req_dp_p0_mag_fc_sds_harden : 1;          /* [1] */
        u32 srst_req_tts_pma_tx_p0_mag_fc_sds_harden : 1;  /* [2] */
        u32 srst_req_fc_h_64b_tx_p0_mag_fc_sds_harden : 1; /* [3] */
        u32 srst_req_fc_l_8g_tx_p0_mag_fc_sds_harden : 1;  /* [4] */
        u32 srst_req_fc_l_16g_tx_p0_mag_fc_sds_harden : 1; /* [5] */
        u32 srst_req_tts_tx_p0_mag_fc_sds_harden : 1;      /* [6] */
        u32 srst_req_fc_h_tx_p0_mag_fc_sds_harden : 1;     /* [7] */
        u32 srst_req_endec_tx_p0_mag_fc_sds_harden : 1;    /* [8] */
        u32 srst_req_tts_pma_rx_p0_mag_fc_sds_harden : 1;  /* [9] */
        u32 srst_req_fc_h_64b_rx_p0_mag_fc_sds_harden : 1; /* [10] */
        u32 srst_req_fc_l_8g_rx_p0_mag_fc_sds_harden : 1;  /* [11] */
        u32 srst_req_fc_l_16g_rx_p0_mag_fc_sds_harden : 1; /* [12] */
        u32 srst_req_tts_rx_p0_mag_fc_sds_harden : 1;      /* [13] */
        u32 srst_req_fc_h_rx_p0_mag_fc_sds_harden : 1;     /* [14] */
        u32 srst_req_endec_rx_p0_mag_fc_sds_harden : 1;    /* [15] */
        u32 srst_req_lpsm_p0_mag_fc_sds_harden : 1;        /* [16] */
        u32 srst_req_bm8g_p0_mag_fc_sds_harden : 1;        /* [17] */
        u32 srst_req_psm_p0_mag_fc_sds_harden : 1;         /* [18] */
        u32 srst_req_bm_p0_mag_fc_sds_harden : 1;          /* [19] */
        u32 rsv_29 : 12;                                   /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_srst_req_mag_fc_sds_harden_p0_u;

/* Define the union csr_icg_en_mag_fc_sds_harden_p1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_fc_ua_p1_mag_fc_sds_harden : 1;          /* [0] */
        u32 icg_en_dp_p1_mag_fc_sds_harden : 1;             /* [1] */
        u32 icg_en_tts_pma_tx_p1_mag_fc_sds_harden : 1;     /* [2] */
        u32 icg_en_fc_h_64b_tx_p1_mag_fc_sds_harden : 1;    /* [3] */
        u32 icg_en_fc_l_8g_tx_p1_mag_fc_sds_harden : 1;     /* [4] */
        u32 icg_en_fc_l_16g_tx_p1_mag_fc_sds_harden : 1;    /* [5] */
        u32 icg_en_tts_tx_p1_mag_fc_sds_harden : 1;         /* [6] */
        u32 icg_en_fc_h_tx_p1_mag_fc_sds_harden : 1;        /* [7] */
        u32 icg_en_endec_tx_p1_mag_fc_sds_harden : 1;       /* [8] */
        u32 icg_en_tts_pma_rx_p1_mag_fc_sds_harden : 1;     /* [9] */
        u32 icg_en_fc_h_64b_rx_p1_mag_fc_sds_harden : 1;    /* [10] */
        u32 icg_en_fc_l_8g_rx_p1_mag_fc_sds_harden : 1;     /* [11] */
        u32 icg_en_fc_l_16g_rx_p1_mag_fc_sds_harden : 1;    /* [12] */
        u32 icg_en_tts_rx_p1_mag_fc_sds_harden : 1;         /* [13] */
        u32 icg_en_fc_h_rx_p1_mag_fc_sds_harden : 1;        /* [14] */
        u32 icg_en_endec_rx_p1_mag_fc_sds_harden : 1;       /* [15] */
        u32 icg_en_lpsm_p1_mag_fc_sds_harden : 1;           /* [16] */
        u32 icg_en_bm8g_p1_mag_fc_sds_harden : 1;           /* [17] */
        u32 icg_en_psm_p1_mag_fc_sds_harden : 1;            /* [18] */
        u32 icg_en_bm_p1_mag_fc_sds_harden : 1;             /* [19] */
        u32 fc_p1_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */
        u32 fc_p1_mclk_sel_mag_fc_sds_harden : 1;           /* [21] */
        u32 fc_p1_bufman_p2p_mode_mag_fc_sds_harden : 1;    /* [22] */
        u32 fc_p1_mode_mag_fc_sds_harden : 3;               /* [25:23] */
        u32 rsv_31 : 6;                                     /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_icg_en_mag_fc_sds_harden_p1_u;

/* Define the union csr_srst_req_mag_fc_sds_harden_p1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_fc_ua_p1_mag_fc_sds_harden : 1;       /* [0] */
        u32 srst_req_dp_p1_mag_fc_sds_harden : 1;          /* [1] */
        u32 srst_req_tts_pma_tx_p1_mag_fc_sds_harden : 1;  /* [2] */
        u32 srst_req_fc_h_64b_tx_p1_mag_fc_sds_harden : 1; /* [3] */
        u32 srst_req_fc_l_8g_tx_p1_mag_fc_sds_harden : 1;  /* [4] */
        u32 srst_req_fc_l_16g_tx_p1_mag_fc_sds_harden : 1; /* [5] */
        u32 srst_req_tts_tx_p1_mag_fc_sds_harden : 1;      /* [6] */
        u32 srst_req_fc_h_tx_p1_mag_fc_sds_harden : 1;     /* [7] */
        u32 srst_req_endec_tx_p1_mag_fc_sds_harden : 1;    /* [8] */
        u32 srst_req_tts_pma_rx_p1_mag_fc_sds_harden : 1;  /* [9] */
        u32 srst_req_fc_h_64b_rx_p1_mag_fc_sds_harden : 1; /* [10] */
        u32 srst_req_fc_l_8g_rx_p1_mag_fc_sds_harden : 1;  /* [11] */
        u32 srst_req_fc_l_16g_rx_p1_mag_fc_sds_harden : 1; /* [12] */
        u32 srst_req_tts_rx_p1_mag_fc_sds_harden : 1;      /* [13] */
        u32 srst_req_fc_h_rx_p1_mag_fc_sds_harden : 1;     /* [14] */
        u32 srst_req_endec_rx_p1_mag_fc_sds_harden : 1;    /* [15] */
        u32 srst_req_lpsm_p1_mag_fc_sds_harden : 1;        /* [16] */
        u32 srst_req_bm8g_p1_mag_fc_sds_harden : 1;        /* [17] */
        u32 srst_req_psm_p1_mag_fc_sds_harden : 1;         /* [18] */
        u32 srst_req_bm_p1_mag_fc_sds_harden : 1;          /* [19] */
        u32 rsv_33 : 12;                                   /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_srst_req_mag_fc_sds_harden_p1_u;

/* Define the union csr_icg_en_mag_fc_sds_harden_p2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_fc_ua_p2_mag_fc_sds_harden : 1;          /* [0] */
        u32 icg_en_dp_p2_mag_fc_sds_harden : 1;             /* [1] */
        u32 icg_en_tts_pma_tx_p2_mag_fc_sds_harden : 1;     /* [2] */
        u32 icg_en_fc_h_64b_tx_p2_mag_fc_sds_harden : 1;    /* [3] */
        u32 icg_en_fc_l_8g_tx_p2_mag_fc_sds_harden : 1;     /* [4] */
        u32 icg_en_fc_l_16g_tx_p2_mag_fc_sds_harden : 1;    /* [5] */
        u32 icg_en_tts_tx_p2_mag_fc_sds_harden : 1;         /* [6] */
        u32 icg_en_fc_h_tx_p2_mag_fc_sds_harden : 1;        /* [7] */
        u32 icg_en_endec_tx_p2_mag_fc_sds_harden : 1;       /* [8] */
        u32 icg_en_tts_pma_rx_p2_mag_fc_sds_harden : 1;     /* [9] */
        u32 icg_en_fc_h_64b_rx_p2_mag_fc_sds_harden : 1;    /* [10] */
        u32 icg_en_fc_l_8g_rx_p2_mag_fc_sds_harden : 1;     /* [11] */
        u32 icg_en_fc_l_16g_rx_p2_mag_fc_sds_harden : 1;    /* [12] */
        u32 icg_en_tts_rx_p2_mag_fc_sds_harden : 1;         /* [13] */
        u32 icg_en_fc_h_rx_p2_mag_fc_sds_harden : 1;        /* [14] */
        u32 icg_en_endec_rx_p2_mag_fc_sds_harden : 1;       /* [15] */
        u32 icg_en_lpsm_p2_mag_fc_sds_harden : 1;           /* [16] */
        u32 icg_en_bm8g_p2_mag_fc_sds_harden : 1;           /* [17] */
        u32 icg_en_psm_p2_mag_fc_sds_harden : 1;            /* [18] */
        u32 icg_en_bm_p2_mag_fc_sds_harden : 1;             /* [19] */
        u32 fc_p2_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */
        u32 fc_p2_mclk_sel_mag_fc_sds_harden : 1;           /* [21] */
        u32 fc_p2_bufman_p2p_mode_mag_fc_sds_harden : 1;    /* [22] */
        u32 fc_p2_mode_mag_fc_sds_harden : 3;               /* [25:23] */
        u32 rsv_35 : 6;                                     /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_icg_en_mag_fc_sds_harden_p2_u;

/* Define the union csr_srst_req_mag_fc_sds_harden_p2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_fc_ua_p2_mag_fc_sds_harden : 1;       /* [0] */
        u32 srst_req_dp_p2_mag_fc_sds_harden : 1;          /* [1] */
        u32 srst_req_tts_pma_tx_p2_mag_fc_sds_harden : 1;  /* [2] */
        u32 srst_req_fc_h_64b_tx_p2_mag_fc_sds_harden : 1; /* [3] */
        u32 srst_req_fc_l_8g_tx_p2_mag_fc_sds_harden : 1;  /* [4] */
        u32 srst_req_fc_l_16g_tx_p2_mag_fc_sds_harden : 1; /* [5] */
        u32 srst_req_tts_tx_p2_mag_fc_sds_harden : 1;      /* [6] */
        u32 srst_req_fc_h_tx_p2_mag_fc_sds_harden : 1;     /* [7] */
        u32 srst_req_endec_tx_p2_mag_fc_sds_harden : 1;    /* [8] */
        u32 srst_req_tts_pma_rx_p2_mag_fc_sds_harden : 1;  /* [9] */
        u32 srst_req_fc_h_64b_rx_p2_mag_fc_sds_harden : 1; /* [10] */
        u32 srst_req_fc_l_8g_rx_p2_mag_fc_sds_harden : 1;  /* [11] */
        u32 srst_req_fc_l_16g_rx_p2_mag_fc_sds_harden : 1; /* [12] */
        u32 srst_req_tts_rx_p2_mag_fc_sds_harden : 1;      /* [13] */
        u32 srst_req_fc_h_rx_p2_mag_fc_sds_harden : 1;     /* [14] */
        u32 srst_req_endec_rx_p2_mag_fc_sds_harden : 1;    /* [15] */
        u32 srst_req_lpsm_p2_mag_fc_sds_harden : 1;        /* [16] */
        u32 srst_req_bm8g_p2_mag_fc_sds_harden : 1;        /* [17] */
        u32 srst_req_psm_p2_mag_fc_sds_harden : 1;         /* [18] */
        u32 srst_req_bm_p2_mag_fc_sds_harden : 1;          /* [19] */
        u32 rsv_37 : 12;                                   /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_srst_req_mag_fc_sds_harden_p2_u;

/* Define the union csr_icg_en_mag_fc_sds_harden_p3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_fc_ua_p3_mag_fc_sds_harden : 1;          /* [0] */
        u32 icg_en_dp_p3_mag_fc_sds_harden : 1;             /* [1] */
        u32 icg_en_tts_pma_tx_p3_mag_fc_sds_harden : 1;     /* [2] */
        u32 icg_en_fc_h_64b_tx_p3_mag_fc_sds_harden : 1;    /* [3] */
        u32 icg_en_fc_l_8g_tx_p3_mag_fc_sds_harden : 1;     /* [4] */
        u32 icg_en_fc_l_16g_tx_p3_mag_fc_sds_harden : 1;    /* [5] */
        u32 icg_en_tts_tx_p3_mag_fc_sds_harden : 1;         /* [6] */
        u32 icg_en_fc_h_tx_p3_mag_fc_sds_harden : 1;        /* [7] */
        u32 icg_en_endec_tx_p3_mag_fc_sds_harden : 1;       /* [8] */
        u32 icg_en_tts_pma_rx_p3_mag_fc_sds_harden : 1;     /* [9] */
        u32 icg_en_fc_h_64b_rx_p3_mag_fc_sds_harden : 1;    /* [10] */
        u32 icg_en_fc_l_8g_rx_p3_mag_fc_sds_harden : 1;     /* [11] */
        u32 icg_en_fc_l_16g_rx_p3_mag_fc_sds_harden : 1;    /* [12] */
        u32 icg_en_tts_rx_p3_mag_fc_sds_harden : 1;         /* [13] */
        u32 icg_en_fc_h_rx_p3_mag_fc_sds_harden : 1;        /* [14] */
        u32 icg_en_endec_rx_p3_mag_fc_sds_harden : 1;       /* [15] */
        u32 icg_en_lpsm_p3_mag_fc_sds_harden : 1;           /* [16] */
        u32 icg_en_bm8g_p3_mag_fc_sds_harden : 1;           /* [17] */
        u32 icg_en_psm_p3_mag_fc_sds_harden : 1;            /* [18] */
        u32 icg_en_bm_p3_mag_fc_sds_harden : 1;             /* [19] */
        u32 fc_p3_bufman_16g_clk_sel_mag_fc_sds_harden : 1; /* [20] */
        u32 fc_p3_mclk_sel_mag_fc_sds_harden : 1;           /* [21] */
        u32 fc_p3_bufman_p2p_mode_mag_fc_sds_harden : 1;    /* [22] */
        u32 fc_p3_mode_mag_fc_sds_harden : 3;               /* [25:23] */
        u32 rsv_39 : 6;                                     /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_icg_en_mag_fc_sds_harden_p3_u;

/* Define the union csr_srst_req_mag_fc_sds_harden_p3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_fc_ua_p3_mag_fc_sds_harden : 1;       /* [0] */
        u32 srst_req_dp_p3_mag_fc_sds_harden : 1;          /* [1] */
        u32 srst_req_tts_pma_tx_p3_mag_fc_sds_harden : 1;  /* [2] */
        u32 srst_req_fc_h_64b_tx_p3_mag_fc_sds_harden : 1; /* [3] */
        u32 srst_req_fc_l_8g_tx_p3_mag_fc_sds_harden : 1;  /* [4] */
        u32 srst_req_fc_l_16g_tx_p3_mag_fc_sds_harden : 1; /* [5] */
        u32 srst_req_tts_tx_p3_mag_fc_sds_harden : 1;      /* [6] */
        u32 srst_req_fc_h_tx_p3_mag_fc_sds_harden : 1;     /* [7] */
        u32 srst_req_endec_tx_p3_mag_fc_sds_harden : 1;    /* [8] */
        u32 srst_req_tts_pma_rx_p3_mag_fc_sds_harden : 1;  /* [9] */
        u32 srst_req_fc_h_64b_rx_p3_mag_fc_sds_harden : 1; /* [10] */
        u32 srst_req_fc_l_8g_rx_p3_mag_fc_sds_harden : 1;  /* [11] */
        u32 srst_req_fc_l_16g_rx_p3_mag_fc_sds_harden : 1; /* [12] */
        u32 srst_req_tts_rx_p3_mag_fc_sds_harden : 1;      /* [13] */
        u32 srst_req_fc_h_rx_p3_mag_fc_sds_harden : 1;     /* [14] */
        u32 srst_req_endec_rx_p3_mag_fc_sds_harden : 1;    /* [15] */
        u32 srst_req_lpsm_p3_mag_fc_sds_harden : 1;        /* [16] */
        u32 srst_req_bm8g_p3_mag_fc_sds_harden : 1;        /* [17] */
        u32 srst_req_psm_p3_mag_fc_sds_harden : 1;         /* [18] */
        u32 srst_req_bm_p3_mag_fc_sds_harden : 1;          /* [19] */
        u32 rsv_41 : 12;                                   /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_srst_req_mag_fc_sds_harden_p3_u;

/* Define the union csr_ring_sta_smf0_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_smf0_harden : 10;     /* [9:0] */
        u32 qpc_rs_nd_pe_crdt_sta_smf0_harden : 10; /* [19:10] */
        u32 rsv_43 : 12;                            /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_smf0_harden_u;

/* Define the union csr_ring_sta_smf1_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_smf1_harden : 10;     /* [9:0] */
        u32 qpc_rs_nd_pe_crdt_sta_smf1_harden : 10; /* [19:10] */
        u32 rsv_45 : 12;                            /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_smf1_harden_u;

/* Define the union csr_ring_sta_stftile0_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_stftile0_harden : 10;     /* [9:0] */
        u32 qpc_rs_nd_pe_crdt_sta_stftile0_harden : 10; /* [19:10] */
        u32 rsv_47 : 12;                                /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_stftile0_harden_u;

/* Define the union csr_ring_sta_stftile1_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_stftile1_harden : 10;     /* [9:0] */
        u32 qpc_rs_nd_pe_crdt_sta_stftile1_harden : 10; /* [19:10] */
        u32 rsv_49 : 12;                                /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_stftile1_harden_u;

/* Define the union csr_ring_sta_ipsurxpetx_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_ipsurx_petx_harden : 10; /* [9:0] */
        u32 rsv_51 : 22;                               /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_ipsurxpetx_harden_u;

/* Define the union csr_ring_sta_ts_harden_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rs_nd_pe_crdt_sta_ts_harden : 10; /* [9:0] */
        u32 rsv_53 : 22;                      /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ring_sta_ts_harden_u;

/* Define the union csr_smf0_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 smf_iso_en_smf0_harden : 1;        /* [0] */
        u32 smf_mtcmos_pwr_on_smf0_harden : 1; /* [1] */
        u32 srst_req_wol_por_smf0_harden : 1;  /* [2] */
        u32 srst_req_wol_comb_smf0_harden : 1; /* [3] */
        u32 wol_rst_sel_smf0_harden : 1;       /* [4] */
        u32 rsv_55 : 27;                       /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_smf0_power_cfg_u;

/* Define the union csr_smf0_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 smf_mtcmos_pwr_ack_smf0_harden : 1; /* [0] */
        u32 rsv_57 : 31;                        /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_smf0_power_ack_u;

/* Define the union csr_smf1_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 smf_iso_en_smf1_harden : 1;        /* [0] */
        u32 smf_mtcmos_pwr_on_smf1_harden : 1; /* [1] */
        u32 srst_req_wol_por_smf1_harden : 1;  /* [2] */
        u32 srst_req_wol_comb_smf1_harden : 1; /* [3] */
        u32 wol_rst_sel_smf1_harden : 1;       /* [4] */
        u32 rsv_59 : 27;                       /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_smf1_power_cfg_u;

/* Define the union csr_smf1_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 smf_mtcmos_pwr_ack_smf1_harden : 1; /* [0] */
        u32 rsv_61 : 31;                        /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_smf1_power_ack_u;

/* Define the union csr_ts_power_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ts_harden_iso_en : 1;            /* [0] */
        u32 ts_harden_mtcmos_pwr_on : 1;     /* [1] */
        u32 ts_harden_srst_req_wol_por : 1;  /* [2] */
        u32 ts_harden_srst_req_wol_comb : 1; /* [3] */
        u32 ts_harden_wol_rst_sel : 1;       /* [4] */
        u32 rsv_63 : 27;                     /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ts_power_cfg_u;

/* Define the union csr_ts_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ts_harden_pwr_ack : 1; /* [0] */
        u32 rsv_65 : 31;           /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_ts_power_ack_u;

/* Define the union csr_stftile0_power_cfg_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tile_pd0_wrap_iso_en_stftile0 : 1;        /* [0] */
        u32 tile_pd0_wrap_mtcmos_pwr_on_stftile0 : 1; /* [1] */
        u32 tile_pd1_wrap_iso_en_stftile0 : 1;        /* [2] */
        u32 tile_pd1_wrap_mtcmos_pwr_on_stftile0 : 1; /* [3] */
        u32 tile_pd2_wrap_iso_en_stftile0 : 1;        /* [4] */
        u32 tile_pd2_wrap_mtcmos_pwr_on_stftile0 : 1; /* [5] */
        u32 tile_pd3_wrap_iso_en_stftile0 : 1;        /* [6] */
        u32 tile_pd3_wrap_mtcmos_pwr_on_stftile0 : 1; /* [7] */
        u32 tile_pd4_wrap_iso_en_stftile0 : 1;        /* [8] */
        u32 tile_pd4_wrap_mtcmos_pwr_on_stftile0 : 1; /* [9] */
        u32 tile_pd5_wrap_iso_en_stftile0 : 1;        /* [10] */
        u32 tile_pd5_wrap_mtcmos_pwr_on_stftile0 : 1; /* [11] */
        u32 tile_qcm_bypass_stftile0 : 6;             /* [17:12] */
        u32 rsv_67 : 14;                              /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stftile0_power_cfg_0_u;

/* Define the union csr_stftile0_power_cfg_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_wol_por_stftile0_qcm0 : 1;  /* [0] */
        u32 srst_req_wol_comb_stftile0_qcm0 : 1; /* [1] */
        u32 wol_rst_sel_stftile0_qcm0 : 1;       /* [2] */
        u32 srst_req_wol_por_stftile0_qcm1 : 1;  /* [3] */
        u32 srst_req_wol_comb_stftile0_qcm1 : 1; /* [4] */
        u32 wol_rst_sel_stftile0_qcm1 : 1;       /* [5] */
        u32 srst_req_wol_por_stftile0_qcm2 : 1;  /* [6] */
        u32 srst_req_wol_comb_stftile0_qcm2 : 1; /* [7] */
        u32 wol_rst_sel_stftile0_qcm2 : 1;       /* [8] */
        u32 srst_req_wol_por_stftile0_qcm3 : 1;  /* [9] */
        u32 srst_req_wol_comb_stftile0_qcm3 : 1; /* [10] */
        u32 wol_rst_sel_stftile0_qcm3 : 1;       /* [11] */
        u32 srst_req_wol_por_stftile0_qcm4 : 1;  /* [12] */
        u32 srst_req_wol_comb_stftile0_qcm4 : 1; /* [13] */
        u32 wol_rst_sel_stftile0_qcm4 : 1;       /* [14] */
        u32 srst_req_wol_por_stftile0_qcm5 : 1;  /* [15] */
        u32 srst_req_wol_comb_stftile0_qcm5 : 1; /* [16] */
        u32 wol_rst_sel_stftile0_qcm5 : 1;       /* [17] */
        u32 rsv_69 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stftile0_power_cfg_1_u;

/* Define the union csr_stftile0_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tile_pd0_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [0] */
        u32 tile_pd1_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [1] */
        u32 tile_pd2_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [2] */
        u32 tile_pd3_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [3] */
        u32 tile_pd4_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [4] */
        u32 tile_pd5_wrap_mtcmos_pwr_ack_stftile0 : 1; /* [5] */
        u32 rsv_71 : 26;                               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stftile0_power_ack_u;

/* Define the union csr_stftile1_power_cfg_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tile_pd0_wrap_iso_en_stftile1 : 1;        /* [0] */
        u32 tile_pd0_wrap_mtcmos_pwr_on_stftile1 : 1; /* [1] */
        u32 tile_pd1_wrap_iso_en_stftile1 : 1;        /* [2] */
        u32 tile_pd1_wrap_mtcmos_pwr_on_stftile1 : 1; /* [3] */
        u32 tile_pd2_wrap_iso_en_stftile1 : 1;        /* [4] */
        u32 tile_pd2_wrap_mtcmos_pwr_on_stftile1 : 1; /* [5] */
        u32 tile_pd3_wrap_iso_en_stftile1 : 1;        /* [6] */
        u32 tile_pd3_wrap_mtcmos_pwr_on_stftile1 : 1; /* [7] */
        u32 tile_pd4_wrap_iso_en_stftile1 : 1;        /* [8] */
        u32 tile_pd4_wrap_mtcmos_pwr_on_stftile1 : 1; /* [9] */
        u32 tile_pd5_wrap_iso_en_stftile1 : 1;        /* [10] */
        u32 tile_pd5_wrap_mtcmos_pwr_on_stftile1 : 1; /* [11] */
        u32 tile_qcm_bypass_stftile1 : 6;             /* [17:12] */
        u32 rsv_73 : 14;                              /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stftile1_power_cfg_0_u;

/* Define the union csr_stftile1_power_cfg_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 srst_req_wol_por_stftile1_qcm0 : 1;  /* [0] */
        u32 srst_req_wol_comb_stftile1_qcm0 : 1; /* [1] */
        u32 wol_rst_sel_stftile1_qcm0 : 1;       /* [2] */
        u32 srst_req_wol_por_stftile1_qcm1 : 1;  /* [3] */
        u32 srst_req_wol_comb_stftile1_qcm1 : 1; /* [4] */
        u32 wol_rst_sel_stftile1_qcm1 : 1;       /* [5] */
        u32 srst_req_wol_por_stftile1_qcm2 : 1;  /* [6] */
        u32 srst_req_wol_comb_stftile1_qcm2 : 1; /* [7] */
        u32 wol_rst_sel_stftile1_qcm2 : 1;       /* [8] */
        u32 srst_req_wol_por_stftile1_qcm3 : 1;  /* [9] */
        u32 srst_req_wol_comb_stftile1_qcm3 : 1; /* [10] */
        u32 wol_rst_sel_stftile1_qcm3 : 1;       /* [11] */
        u32 srst_req_wol_por_stftile1_qcm4 : 1;  /* [12] */
        u32 srst_req_wol_comb_stftile1_qcm4 : 1; /* [13] */
        u32 wol_rst_sel_stftile1_qcm4 : 1;       /* [14] */
        u32 srst_req_wol_por_stftile1_qcm5 : 1;  /* [15] */
        u32 srst_req_wol_comb_stftile1_qcm5 : 1; /* [16] */
        u32 wol_rst_sel_stftile1_qcm5 : 1;       /* [17] */
        u32 rsv_75 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stftile1_power_cfg_1_u;

/* Define the union csr_stftile1_power_ack_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tile_pd0_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [0] */
        u32 tile_pd1_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [1] */
        u32 tile_pd2_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [2] */
        u32 tile_pd3_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [3] */
        u32 tile_pd4_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [4] */
        u32 tile_pd5_wrap_mtcmos_pwr_ack_stftile1 : 1; /* [5] */
        u32 rsv_77 : 26;                               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_stftile1_power_ack_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_crg_cfg_smf0_harden_u crg_cfg_smf0_harden;                     /* 0 */
    volatile csr_crg_cfg_smf1_harden_u crg_cfg_smf1_harden;                     /* 4 */
    volatile csr_crg_cfg_stftile0_harden_u crg_cfg_stftile0_harden;             /* 8 */
    volatile csr_crg_cfg_stftile1_harden_u crg_cfg_stftile1_harden;             /* C */
    volatile csr_crg_cfg_ipsurx_petx_harden_u crg_cfg_ipsurx_petx_harden;       /* 10 */
    volatile csr_crg_cfg_ts_harden_u crg_cfg_ts_harden;                         /* 14 */
    volatile csr_crg_cfg_mag_fc_sds_harden_0_u crg_cfg_mag_fc_sds_harden_0;     /* 18 */
    volatile csr_crg_cfg_mag_fc_sds_harden_1_u crg_cfg_mag_fc_sds_harden_1;     /* 1C */
    volatile csr_crg_cfg_mag_fc_sds_harden_2_u crg_cfg_mag_fc_sds_harden_2;     /* 20 */
    volatile csr_crg_cfg_mag_fc_sds_harden_3_u crg_cfg_mag_fc_sds_harden_3;     /* 24 */
    volatile csr_crg_cfg_mag_fc_sds_harden_4_u crg_cfg_mag_fc_sds_harden_4;     /* 28 */
    volatile csr_crg_cfg_mag_fc_sds_harden_5_u crg_cfg_mag_fc_sds_harden_5;     /* 2C */
    volatile csr_crg_cfg_mag_fc_sds_harden_6_u crg_cfg_mag_fc_sds_harden_6;     /* 30 */
    volatile csr_crg_cfg_mag_fc_sds_harden_7_u crg_cfg_mag_fc_sds_harden_7;     /* 34 */
    volatile csr_crg_cfg_mag_fc_sds_harden_8_u crg_cfg_mag_fc_sds_harden_8;     /* 38 */
    volatile csr_crg_cfg_mag_fc_sds_harden_9_u crg_cfg_mag_fc_sds_harden_9;     /* 3C */
    volatile csr_crg_cfg_mag_fc_sds_harden_10_u crg_cfg_mag_fc_sds_harden_10;   /* 40 */
    volatile csr_crg_cfg_mag_fc_sds_harden_11_u crg_cfg_mag_fc_sds_harden_11;   /* 44 */
    volatile csr_icg_en_mag_fc_sds_harden_p0_u icg_en_mag_fc_sds_harden_p0;     /* 48 */
    volatile csr_srst_req_mag_fc_sds_harden_p0_u srst_req_mag_fc_sds_harden_p0; /* 4C */
    volatile csr_icg_en_mag_fc_sds_harden_p1_u icg_en_mag_fc_sds_harden_p1;     /* 50 */
    volatile csr_srst_req_mag_fc_sds_harden_p1_u srst_req_mag_fc_sds_harden_p1; /* 54 */
    volatile csr_icg_en_mag_fc_sds_harden_p2_u icg_en_mag_fc_sds_harden_p2;     /* 58 */
    volatile csr_srst_req_mag_fc_sds_harden_p2_u srst_req_mag_fc_sds_harden_p2; /* 5C */
    volatile csr_icg_en_mag_fc_sds_harden_p3_u icg_en_mag_fc_sds_harden_p3;     /* 60 */
    volatile csr_srst_req_mag_fc_sds_harden_p3_u srst_req_mag_fc_sds_harden_p3; /* 64 */
    volatile csr_ring_sta_smf0_harden_u ring_sta_smf0_harden;                   /* 68 */
    volatile csr_ring_sta_smf1_harden_u ring_sta_smf1_harden;                   /* 6C */
    volatile csr_ring_sta_stftile0_harden_u ring_sta_stftile0_harden;           /* 70 */
    volatile csr_ring_sta_stftile1_harden_u ring_sta_stftile1_harden;           /* 74 */
    volatile csr_ring_sta_ipsurxpetx_harden_u ring_sta_ipsurxpetx_harden;       /* 78 */
    volatile csr_ring_sta_ts_harden_u ring_sta_ts_harden;                       /* 7C */
    volatile csr_smf0_power_cfg_u smf0_power_cfg;                               /* 80 */
    volatile csr_smf0_power_ack_u smf0_power_ack;                               /* 84 */
    volatile csr_smf1_power_cfg_u smf1_power_cfg;                               /* 88 */
    volatile csr_smf1_power_ack_u smf1_power_ack;                               /* 8C */
    volatile csr_ts_power_cfg_u ts_power_cfg;                                   /* 90 */
    volatile csr_ts_power_ack_u ts_power_ack;                                   /* 94 */
    volatile csr_stftile0_power_cfg_0_u stftile0_power_cfg_0;                   /* 98 */
    volatile csr_stftile0_power_cfg_1_u stftile0_power_cfg_1;                   /* 9C */
    volatile csr_stftile0_power_ack_u stftile0_power_ack;                       /* A0 */
    volatile csr_stftile1_power_cfg_0_u stftile1_power_cfg_0;                   /* A4 */
    volatile csr_stftile1_power_cfg_1_u stftile1_power_cfg_1;                   /* A8 */
    volatile csr_stftile1_power_ack_u stftile1_power_ack;                       /* AC */
} S_smf0_harden_node_csr_REGS_TYPE;

/* Declare the struct pointor of the module smf0_harden_node_csr */
extern volatile S_smf0_harden_node_csr_REGS_TYPE *gopsmf0_harden_node_csrAllReg;

/* Declare the functions that set the member value */
int iSetCRG_CFG_SMF0_HARDEN_icg_en_ring_smf0_harden(unsigned int uicg_en_ring_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_icg_en_smf_smf0_harden(unsigned int uicg_en_smf_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_icg_en_smf_div2_smf0_harden(unsigned int uicg_en_smf_div2_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_icg_en_virtio_core_smf0_harden(unsigned int uicg_en_virtio_core_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_icg_en_smeg_smf0_harden(unsigned int uicg_en_smeg_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_srst_req_ring_smf0_harden(unsigned int usrst_req_ring_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_srst_req_smf_smf0_harden(unsigned int usrst_req_smf_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_srst_req_virtio_core_smf0_harden(unsigned int usrst_req_virtio_core_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_srst_req_smf_div2_smf0_harden(unsigned int usrst_req_smf_div2_smf0_harden);
int iSetCRG_CFG_SMF0_HARDEN_srst_req_smeg_smf0_harden(unsigned int usrst_req_smeg_smf0_harden);
int iSetCRG_CFG_SMF1_HARDEN_icg_en_ring_smf1_harden(unsigned int uicg_en_ring_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_icg_en_smf_smf1_harden(unsigned int uicg_en_smf_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_icg_en_smf_div2_smf1_harden(unsigned int uicg_en_smf_div2_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_icg_en_virtio_core_smf1_harden(unsigned int uicg_en_virtio_core_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_icg_en_smeg_smf1_harden(unsigned int uicg_en_smeg_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_srst_req_ring_smf1_harden(unsigned int usrst_req_ring_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_srst_req_smf_smf1_harden(unsigned int usrst_req_smf_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_srst_req_virtio_core_smf1_harden(unsigned int usrst_req_virtio_core_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_srst_req_smf_div2_smf1_harden(unsigned int usrst_req_smf_div2_smf1_harden);
int iSetCRG_CFG_SMF1_HARDEN_srst_req_smeg_smf1_harden(unsigned int usrst_req_smeg_smf1_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_qcm_stftile0_harden(unsigned int uicg_en_qcm_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_tile_stftile0_harden(unsigned int uicg_en_tile_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_tile_div2_stftile0_harden(unsigned int uicg_en_tile_div2_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_icg_en_ring_stftile0_harden(unsigned int uicg_en_ring_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_cnb_stftile0_harden(unsigned int usrst_req_cnb_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_l2i_stftile0_harden(unsigned int usrst_req_l2i_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_mbist_stftile0_harden(unsigned int usrst_req_mbist_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_mtc_stftile0_harden(unsigned int usrst_req_mtc_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_qcm_stftile0_harden(unsigned int usrst_req_qcm_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_rep_stftile0_harden(unsigned int usrst_req_rep_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_ring_stftile0_harden(unsigned int usrst_req_ring_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_tiu_stftile0_harden(unsigned int usrst_req_tiu_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_srst_req_tou_stftile0_harden(unsigned int usrst_req_tou_stftile0_harden);
int iSetCRG_CFG_STFTILE0_HARDEN_tile_sys_clk_sel_stftile0_harden(unsigned int utile_sys_clk_sel_stftile0_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_qcm_stftile1_harden(unsigned int uicg_en_qcm_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_tile_stftile1_harden(unsigned int uicg_en_tile_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_tile_div2_stftile1_harden(unsigned int uicg_en_tile_div2_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_icg_en_ring_stftile1_harden(unsigned int uicg_en_ring_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_cnb_stftile1_harden(unsigned int usrst_req_cnb_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_l2i_stftile1_harden(unsigned int usrst_req_l2i_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_mbist_stftile1_harden(unsigned int usrst_req_mbist_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_mtc_stftile1_harden(unsigned int usrst_req_mtc_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_qcm_stftile1_harden(unsigned int usrst_req_qcm_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_rep_stftile1_harden(unsigned int usrst_req_rep_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_ring_stftile1_harden(unsigned int usrst_req_ring_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_tiu_stftile1_harden(unsigned int usrst_req_tiu_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_srst_req_tou_stftile1_harden(unsigned int usrst_req_tou_stftile1_harden);
int iSetCRG_CFG_STFTILE1_HARDEN_tile_sys_clk_sel_stftile1_harden(unsigned int utile_sys_clk_sel_stftile1_harden);
int iSetCRG_CFG_IPSURX_PETX_HARDEN_icg_en_ring_ipsurx_petx_harden(unsigned int uicg_en_ring_ipsurx_petx_harden);
int iSetCRG_CFG_IPSURX_PETX_HARDEN_icg_en_dp_network_ipsurx_petx_harden(
    unsigned int uicg_en_dp_network_ipsurx_petx_harden);
int iSetCRG_CFG_IPSURX_PETX_HARDEN_srst_req_ring_ipsurx_petx_harden(unsigned int usrst_req_ring_ipsurx_petx_harden);
int iSetCRG_CFG_IPSURX_PETX_HARDEN_srst_req_dp_network_ipsurx_petx_harden(
    unsigned int usrst_req_dp_network_ipsurx_petx_harden);
int iSetCRG_CFG_TS_HARDEN_icg_en_ring_ts_harden(unsigned int uicg_en_ring_ts_harden);
int iSetCRG_CFG_TS_HARDEN_icg_en_ts_ts_harden(unsigned int uicg_en_ts_ts_harden);
int iSetCRG_CFG_TS_HARDEN_icg_en_cnb2apb_ts_harden(unsigned int uicg_en_cnb2apb_ts_harden);
int iSetCRG_CFG_TS_HARDEN_srst_req_ring_ts_harden(unsigned int usrst_req_ring_ts_harden);
int iSetCRG_CFG_TS_HARDEN_srst_req_ts_ts_harden(unsigned int usrst_req_ts_ts_harden);
int iSetCRG_CFG_TS_HARDEN_srst_req_cnb2apb_ts_harden(unsigned int usrst_req_cnb2apb_ts_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_apb_chain_mag_fc_sds_harden(
    unsigned int uicg_en_apb_chain_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_mag_mag_fc_sds_harden(unsigned int uicg_en_mag_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_mac_core_mag_fc_sds_harden(unsigned int uicg_en_mac_core_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_mac_ptp_mag_fc_sds_harden(unsigned int uicg_en_mac_ptp_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_an_lt_cfg_mag_fc_sds_harden(
    unsigned int uicg_en_an_lt_cfg_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_led_mag_fc_sds_harden(unsigned int uicg_en_led_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes6_mag_rx_su_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_mag_rx_su_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes7_mag_rx_su_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_mag_rx_su_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_an_core_mag_fc_sds_harden(unsigned int uicg_en_an_core_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes6_mclk_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_mclk_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_serdes7_mclk_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_mclk_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_fc_apb_mag_fc_sds_harden(unsigned int uicg_en_fc_apb_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_dp_com_mag_fc_sds_harden(unsigned int uicg_en_dp_com_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_p01_rx_pma_mag_fc_sds_harden(
    unsigned int uicg_en_p01_rx_pma_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_0_icg_en_p23_rx_pma_mag_fc_sds_harden(
    unsigned int uicg_en_p23_rx_pma_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_apb_chain_mag_fc_sds_harden(
    unsigned int usrst_req_apb_chain_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mag_mag_fc_sds_harden(unsigned int usrst_req_mag_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_core_mag_fc_sds_harden(
    unsigned int usrst_req_mac_core_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_t_mag_fc_sds_harden(unsigned int usrst_req_mac_t_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_ptp_mag_fc_sds_harden(
    unsigned int usrst_req_mac_ptp_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_an_lt_cfg_mag_fc_sds_harden(
    unsigned int usrst_req_an_lt_cfg_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_led_mag_fc_sds_harden(unsigned int usrst_req_led_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_mac_logic_mag_fc_sds_harden(
    unsigned int usrst_req_mac_logic_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_an_core_mag_fc_sds_harden(
    unsigned int usrst_req_an_core_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_fc_apb_mag_fc_sds_harden(unsigned int usrst_req_fc_apb_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_dp_com_mag_fc_sds_harden(unsigned int usrst_req_dp_com_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_p01_rx_pma_mag_fc_sds_harden(
    unsigned int usrst_req_p01_rx_pma_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_1_srst_req_p23_rx_pma_mag_fc_sds_harden(
    unsigned int usrst_req_p23_rx_pma_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_txo_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_txo_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_txo_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_txo_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_rxo_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_rxo_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_rxo_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_rxo_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_pma_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_pma_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_pma_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_pma_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes6_pma_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_pma_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_2_icg_en_serdes7_pma_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_pma_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes6_spi_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_spi_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes7_spi_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_spi_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_lt_spi_mag_fc_sds_harden(unsigned int uicg_en_lt_spi_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes6_mac_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_mac_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_3_icg_en_serdes7_mac_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_mac_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_an_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_an_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_an_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_an_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_lt_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_lt_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_lt_rx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_lt_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_mac_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_mac_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_mac_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_mac_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes6_an_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_an_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_4_icg_en_serdes7_an_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_an_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes6_lt_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_lt_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes7_lt_tx_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_lt_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes6_rxaux_mag_fc_sds_harden(
    unsigned int uicg_en_serdes6_rxaux_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_5_icg_en_serdes7_rxaux_mag_fc_sds_harden(
    unsigned int uicg_en_serdes7_rxaux_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes6_pma_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_pma_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes7_pma_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_pma_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes6_pma_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_pma_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes7_pma_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_pma_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes6_spi_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_spi_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_serdes7_spi_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_spi_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_6_srst_req_lt_spi_mag_fc_sds_harden(unsigned int usrst_req_lt_spi_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_mac_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_mac_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_mac_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_mac_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_an_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_an_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_an_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_an_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_lt_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_lt_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_lt_rx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_lt_rx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes6_mac_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_mac_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_7_srst_req_serdes7_mac_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_mac_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes6_an_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_an_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes7_an_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_an_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes6_lt_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes6_lt_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_serdes7_lt_tx_mag_fc_sds_harden(
    unsigned int usrst_req_serdes7_lt_tx_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_an_rs_mag_fc_sds_harden(unsigned int usrst_req_an_rs_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_8_srst_req_lt_rs_mag_fc_sds_harden(unsigned int usrst_req_lt_rs_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_phy_rx_logic_mag_fc_sds_harden(
    unsigned int usrst_req_phy_rx_logic_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_port_rx_logic_mag_fc_sds_harden(
    unsigned int usrst_req_port_rx_logic_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_phy_tx_logic_mag_fc_sds_harden(
    unsigned int usrst_req_phy_tx_logic_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_9_srst_req_port_tx_logic_mag_fc_sds_harden(
    unsigned int usrst_req_port_tx_logic_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_func_mbist_clk_sel_mag_fc_sds_harden(
    unsigned int ufunc_mbist_clk_sel_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_serdes6_pma_rx_su_clk_sel_mag_fc_sds_harden(
    unsigned int userdes6_pma_rx_su_clk_sel_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_serdes7_pma_rx_su_clk_sel_mag_fc_sds_harden(
    unsigned int userdes7_pma_rx_su_clk_sel_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_p01_pma_rx_clk_sel_mag_fc_sds_harden(
    unsigned int up01_pma_rx_clk_sel_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_10_p23_pma_rx_clk_sel_mag_fc_sds_harden(
    unsigned int up23_pma_rx_clk_sel_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_probe_sds_mag_sel_mag_fc_sds_harden(
    unsigned int uprobe_sds_mag_sel_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_icg_en_probe_mag_fc_sds_harden(unsigned int uicg_en_probe_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_probe_mode_mag_fc_sds_harden(unsigned int uprobe_mode_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_sds_fc_mclk_icg_en_sel_mag_fc_sds_harden(
    unsigned int usds_fc_mclk_icg_en_sel_mag_fc_sds_harden);
int iSetCRG_CFG_MAG_FC_SDS_HARDEN_11_mag_fc_hclk_clk_sel_mag_fc_sds_harden(
    unsigned int umag_fc_hclk_clk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_ua_p0_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_dp_p0_mag_fc_sds_harden(unsigned int uicg_en_dp_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_pma_tx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_tx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_64b_tx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_tx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_8g_tx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_tx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_16g_tx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_tx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_tx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_tts_tx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_tx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_tx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_endec_tx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_endec_tx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_pma_rx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_rx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_64b_rx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_rx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_8g_rx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_rx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_l_16g_rx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_rx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_tts_rx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_tts_rx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_fc_h_rx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_rx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_endec_rx_p0_mag_fc_sds_harden(
    unsigned int uicg_en_endec_rx_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_lpsm_p0_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_bm8g_p0_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_psm_p0_mag_fc_sds_harden(unsigned int uicg_en_psm_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_icg_en_bm_p0_mag_fc_sds_harden(unsigned int uicg_en_bm_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_bufman_16g_clk_sel_mag_fc_sds_harden(
    unsigned int ufc_p0_bufman_16g_clk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p0_mclk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_bufman_p2p_mode_mag_fc_sds_harden(
    unsigned int ufc_p0_bufman_p2p_mode_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P0_fc_p0_mode_mag_fc_sds_harden(unsigned int ufc_p0_mode_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_ua_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_ua_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_dp_p0_mag_fc_sds_harden(unsigned int usrst_req_dp_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_pma_tx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_tx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_64b_tx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_tx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_8g_tx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_tx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_16g_tx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_tx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_tx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_tts_tx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_tx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_tx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_endec_tx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_endec_tx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_pma_rx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_rx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_64b_rx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_rx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_8g_rx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_rx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_l_16g_rx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_rx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_tts_rx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_tts_rx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_fc_h_rx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_rx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_endec_rx_p0_mag_fc_sds_harden(
    unsigned int usrst_req_endec_rx_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_lpsm_p0_mag_fc_sds_harden(
    unsigned int usrst_req_lpsm_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_bm8g_p0_mag_fc_sds_harden(
    unsigned int usrst_req_bm8g_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_psm_p0_mag_fc_sds_harden(
    unsigned int usrst_req_psm_p0_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P0_srst_req_bm_p0_mag_fc_sds_harden(unsigned int usrst_req_bm_p0_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_ua_p1_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_dp_p1_mag_fc_sds_harden(unsigned int uicg_en_dp_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_pma_tx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_tx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_64b_tx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_tx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_8g_tx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_tx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_16g_tx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_tx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_tx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_tts_tx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_tx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_tx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_endec_tx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_endec_tx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_pma_rx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_rx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_64b_rx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_rx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_8g_rx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_rx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_l_16g_rx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_rx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_tts_rx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_tts_rx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_fc_h_rx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_rx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_endec_rx_p1_mag_fc_sds_harden(
    unsigned int uicg_en_endec_rx_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_lpsm_p1_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_bm8g_p1_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_psm_p1_mag_fc_sds_harden(unsigned int uicg_en_psm_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_icg_en_bm_p1_mag_fc_sds_harden(unsigned int uicg_en_bm_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_bufman_16g_clk_sel_mag_fc_sds_harden(
    unsigned int ufc_p1_bufman_16g_clk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p1_mclk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_bufman_p2p_mode_mag_fc_sds_harden(
    unsigned int ufc_p1_bufman_p2p_mode_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P1_fc_p1_mode_mag_fc_sds_harden(unsigned int ufc_p1_mode_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_ua_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_ua_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_dp_p1_mag_fc_sds_harden(unsigned int usrst_req_dp_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_pma_tx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_tx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_64b_tx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_tx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_8g_tx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_tx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_16g_tx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_tx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_tx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_tts_tx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_tx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_tx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_endec_tx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_endec_tx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_pma_rx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_rx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_64b_rx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_rx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_8g_rx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_rx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_l_16g_rx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_rx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_tts_rx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_tts_rx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_fc_h_rx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_rx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_endec_rx_p1_mag_fc_sds_harden(
    unsigned int usrst_req_endec_rx_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_lpsm_p1_mag_fc_sds_harden(
    unsigned int usrst_req_lpsm_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_bm8g_p1_mag_fc_sds_harden(
    unsigned int usrst_req_bm8g_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_psm_p1_mag_fc_sds_harden(
    unsigned int usrst_req_psm_p1_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P1_srst_req_bm_p1_mag_fc_sds_harden(unsigned int usrst_req_bm_p1_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_ua_p2_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_dp_p2_mag_fc_sds_harden(unsigned int uicg_en_dp_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_pma_tx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_tx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_64b_tx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_tx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_8g_tx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_tx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_16g_tx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_tx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_tx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_tts_tx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_tx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_tx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_endec_tx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_endec_tx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_pma_rx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_rx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_64b_rx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_rx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_8g_rx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_rx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_l_16g_rx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_rx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_tts_rx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_tts_rx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_fc_h_rx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_rx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_endec_rx_p2_mag_fc_sds_harden(
    unsigned int uicg_en_endec_rx_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_lpsm_p2_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_bm8g_p2_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_psm_p2_mag_fc_sds_harden(unsigned int uicg_en_psm_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_icg_en_bm_p2_mag_fc_sds_harden(unsigned int uicg_en_bm_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_bufman_16g_clk_sel_mag_fc_sds_harden(
    unsigned int ufc_p2_bufman_16g_clk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p2_mclk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_bufman_p2p_mode_mag_fc_sds_harden(
    unsigned int ufc_p2_bufman_p2p_mode_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P2_fc_p2_mode_mag_fc_sds_harden(unsigned int ufc_p2_mode_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_ua_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_ua_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_dp_p2_mag_fc_sds_harden(unsigned int usrst_req_dp_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_pma_tx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_tx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_64b_tx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_tx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_8g_tx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_tx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_16g_tx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_tx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_tx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_tts_tx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_tx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_tx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_endec_tx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_endec_tx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_pma_rx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_rx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_64b_rx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_rx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_8g_rx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_rx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_l_16g_rx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_rx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_tts_rx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_tts_rx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_fc_h_rx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_rx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_endec_rx_p2_mag_fc_sds_harden(
    unsigned int usrst_req_endec_rx_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_lpsm_p2_mag_fc_sds_harden(
    unsigned int usrst_req_lpsm_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_bm8g_p2_mag_fc_sds_harden(
    unsigned int usrst_req_bm8g_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_psm_p2_mag_fc_sds_harden(
    unsigned int usrst_req_psm_p2_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P2_srst_req_bm_p2_mag_fc_sds_harden(unsigned int usrst_req_bm_p2_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_ua_p3_mag_fc_sds_harden(unsigned int uicg_en_fc_ua_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_dp_p3_mag_fc_sds_harden(unsigned int uicg_en_dp_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_pma_tx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_tx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_64b_tx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_tx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_8g_tx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_tx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_16g_tx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_tx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_tx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_tts_tx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_tx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_tx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_endec_tx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_endec_tx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_pma_rx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_tts_pma_rx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_64b_rx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_64b_rx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_8g_rx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_8g_rx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_l_16g_rx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_l_16g_rx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_tts_rx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_tts_rx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_fc_h_rx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_fc_h_rx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_endec_rx_p3_mag_fc_sds_harden(
    unsigned int uicg_en_endec_rx_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_lpsm_p3_mag_fc_sds_harden(unsigned int uicg_en_lpsm_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_bm8g_p3_mag_fc_sds_harden(unsigned int uicg_en_bm8g_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_psm_p3_mag_fc_sds_harden(unsigned int uicg_en_psm_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_icg_en_bm_p3_mag_fc_sds_harden(unsigned int uicg_en_bm_p3_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_bufman_16g_clk_sel_mag_fc_sds_harden(
    unsigned int ufc_p3_bufman_16g_clk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_mclk_sel_mag_fc_sds_harden(unsigned int ufc_p3_mclk_sel_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_bufman_p2p_mode_mag_fc_sds_harden(
    unsigned int ufc_p3_bufman_p2p_mode_mag_fc_sds_harden);
int iSetICG_EN_MAG_FC_SDS_HARDEN_P3_fc_p3_mode_mag_fc_sds_harden(unsigned int ufc_p3_mode_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_ua_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_ua_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_dp_p3_mag_fc_sds_harden(unsigned int usrst_req_dp_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_pma_tx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_tx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_64b_tx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_tx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_8g_tx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_tx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_16g_tx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_tx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_tx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_tts_tx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_tx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_tx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_endec_tx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_endec_tx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_pma_rx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_tts_pma_rx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_64b_rx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_64b_rx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_8g_rx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_8g_rx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_l_16g_rx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_l_16g_rx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_tts_rx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_tts_rx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_fc_h_rx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_fc_h_rx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_endec_rx_p3_mag_fc_sds_harden(
    unsigned int usrst_req_endec_rx_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_lpsm_p3_mag_fc_sds_harden(
    unsigned int usrst_req_lpsm_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_bm8g_p3_mag_fc_sds_harden(
    unsigned int usrst_req_bm8g_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_psm_p3_mag_fc_sds_harden(
    unsigned int usrst_req_psm_p3_mag_fc_sds_harden);
int iSetSRST_REQ_MAG_FC_SDS_HARDEN_P3_srst_req_bm_p3_mag_fc_sds_harden(unsigned int usrst_req_bm_p3_mag_fc_sds_harden);
int iSetRING_STA_SMF0_HARDEN_rs_nd_pe_crdt_sta_smf0_harden(unsigned int urs_nd_pe_crdt_sta_smf0_harden);
int iSetRING_STA_SMF0_HARDEN_qpc_rs_nd_pe_crdt_sta_smf0_harden(unsigned int uqpc_rs_nd_pe_crdt_sta_smf0_harden);
int iSetRING_STA_SMF1_HARDEN_rs_nd_pe_crdt_sta_smf1_harden(unsigned int urs_nd_pe_crdt_sta_smf1_harden);
int iSetRING_STA_SMF1_HARDEN_qpc_rs_nd_pe_crdt_sta_smf1_harden(unsigned int uqpc_rs_nd_pe_crdt_sta_smf1_harden);
int iSetRING_STA_STFTILE0_HARDEN_rs_nd_pe_crdt_sta_stftile0_harden(unsigned int urs_nd_pe_crdt_sta_stftile0_harden);
int iSetRING_STA_STFTILE0_HARDEN_qpc_rs_nd_pe_crdt_sta_stftile0_harden(
    unsigned int uqpc_rs_nd_pe_crdt_sta_stftile0_harden);
int iSetRING_STA_STFTILE1_HARDEN_rs_nd_pe_crdt_sta_stftile1_harden(unsigned int urs_nd_pe_crdt_sta_stftile1_harden);
int iSetRING_STA_STFTILE1_HARDEN_qpc_rs_nd_pe_crdt_sta_stftile1_harden(
    unsigned int uqpc_rs_nd_pe_crdt_sta_stftile1_harden);
int iSetRING_STA_IPSURXPETX_HARDEN_rs_nd_pe_crdt_sta_ipsurx_petx_harden(
    unsigned int urs_nd_pe_crdt_sta_ipsurx_petx_harden);
int iSetRING_STA_TS_HARDEN_rs_nd_pe_crdt_sta_ts_harden(unsigned int urs_nd_pe_crdt_sta_ts_harden);
int iSetSMF0_POWER_CFG_smf_iso_en_smf0_harden(unsigned int usmf_iso_en_smf0_harden);
int iSetSMF0_POWER_CFG_smf_mtcmos_pwr_on_smf0_harden(unsigned int usmf_mtcmos_pwr_on_smf0_harden);
int iSetSMF0_POWER_CFG_srst_req_wol_por_smf0_harden(unsigned int usrst_req_wol_por_smf0_harden);
int iSetSMF0_POWER_CFG_srst_req_wol_comb_smf0_harden(unsigned int usrst_req_wol_comb_smf0_harden);
int iSetSMF0_POWER_CFG_wol_rst_sel_smf0_harden(unsigned int uwol_rst_sel_smf0_harden);
int iSetSMF0_POWER_ACK_smf_mtcmos_pwr_ack_smf0_harden(unsigned int usmf_mtcmos_pwr_ack_smf0_harden);
int iSetSMF1_POWER_CFG_smf_iso_en_smf1_harden(unsigned int usmf_iso_en_smf1_harden);
int iSetSMF1_POWER_CFG_smf_mtcmos_pwr_on_smf1_harden(unsigned int usmf_mtcmos_pwr_on_smf1_harden);
int iSetSMF1_POWER_CFG_srst_req_wol_por_smf1_harden(unsigned int usrst_req_wol_por_smf1_harden);
int iSetSMF1_POWER_CFG_srst_req_wol_comb_smf1_harden(unsigned int usrst_req_wol_comb_smf1_harden);
int iSetSMF1_POWER_CFG_wol_rst_sel_smf1_harden(unsigned int uwol_rst_sel_smf1_harden);
int iSetSMF1_POWER_ACK_smf_mtcmos_pwr_ack_smf1_harden(unsigned int usmf_mtcmos_pwr_ack_smf1_harden);
int iSetTS_POWER_CFG_ts_harden_iso_en(unsigned int uts_harden_iso_en);
int iSetTS_POWER_CFG_ts_harden_mtcmos_pwr_on(unsigned int uts_harden_mtcmos_pwr_on);
int iSetTS_POWER_CFG_ts_harden_srst_req_wol_por(unsigned int uts_harden_srst_req_wol_por);
int iSetTS_POWER_CFG_ts_harden_srst_req_wol_comb(unsigned int uts_harden_srst_req_wol_comb);
int iSetTS_POWER_CFG_ts_harden_wol_rst_sel(unsigned int uts_harden_wol_rst_sel);
int iSetTS_POWER_ACK_ts_harden_pwr_ack(unsigned int uts_harden_pwr_ack);
int iSetSTFTILE0_POWER_CFG_0_tile_pd0_wrap_iso_en_stftile0(unsigned int utile_pd0_wrap_iso_en_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd0_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd0_wrap_mtcmos_pwr_on_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd1_wrap_iso_en_stftile0(unsigned int utile_pd1_wrap_iso_en_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd1_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd1_wrap_mtcmos_pwr_on_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd2_wrap_iso_en_stftile0(unsigned int utile_pd2_wrap_iso_en_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd2_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd2_wrap_mtcmos_pwr_on_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd3_wrap_iso_en_stftile0(unsigned int utile_pd3_wrap_iso_en_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd3_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd3_wrap_mtcmos_pwr_on_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd4_wrap_iso_en_stftile0(unsigned int utile_pd4_wrap_iso_en_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd4_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd4_wrap_mtcmos_pwr_on_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd5_wrap_iso_en_stftile0(unsigned int utile_pd5_wrap_iso_en_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_pd5_wrap_mtcmos_pwr_on_stftile0(unsigned int utile_pd5_wrap_mtcmos_pwr_on_stftile0);
int iSetSTFTILE0_POWER_CFG_0_tile_qcm_bypass_stftile0(unsigned int utile_qcm_bypass_stftile0);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm0(unsigned int usrst_req_wol_por_stftile0_qcm0);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm0(unsigned int usrst_req_wol_comb_stftile0_qcm0);
int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm0(unsigned int uwol_rst_sel_stftile0_qcm0);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm1(unsigned int usrst_req_wol_por_stftile0_qcm1);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm1(unsigned int usrst_req_wol_comb_stftile0_qcm1);
int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm1(unsigned int uwol_rst_sel_stftile0_qcm1);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm2(unsigned int usrst_req_wol_por_stftile0_qcm2);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm2(unsigned int usrst_req_wol_comb_stftile0_qcm2);
int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm2(unsigned int uwol_rst_sel_stftile0_qcm2);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm3(unsigned int usrst_req_wol_por_stftile0_qcm3);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm3(unsigned int usrst_req_wol_comb_stftile0_qcm3);
int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm3(unsigned int uwol_rst_sel_stftile0_qcm3);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm4(unsigned int usrst_req_wol_por_stftile0_qcm4);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm4(unsigned int usrst_req_wol_comb_stftile0_qcm4);
int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm4(unsigned int uwol_rst_sel_stftile0_qcm4);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_por_stftile0_qcm5(unsigned int usrst_req_wol_por_stftile0_qcm5);
int iSetSTFTILE0_POWER_CFG_1_srst_req_wol_comb_stftile0_qcm5(unsigned int usrst_req_wol_comb_stftile0_qcm5);
int iSetSTFTILE0_POWER_CFG_1_wol_rst_sel_stftile0_qcm5(unsigned int uwol_rst_sel_stftile0_qcm5);
int iSetSTFTILE0_POWER_ACK_tile_pd0_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd0_wrap_mtcmos_pwr_ack_stftile0);
int iSetSTFTILE0_POWER_ACK_tile_pd1_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd1_wrap_mtcmos_pwr_ack_stftile0);
int iSetSTFTILE0_POWER_ACK_tile_pd2_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd2_wrap_mtcmos_pwr_ack_stftile0);
int iSetSTFTILE0_POWER_ACK_tile_pd3_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd3_wrap_mtcmos_pwr_ack_stftile0);
int iSetSTFTILE0_POWER_ACK_tile_pd4_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd4_wrap_mtcmos_pwr_ack_stftile0);
int iSetSTFTILE0_POWER_ACK_tile_pd5_wrap_mtcmos_pwr_ack_stftile0(unsigned int utile_pd5_wrap_mtcmos_pwr_ack_stftile0);
int iSetSTFTILE1_POWER_CFG_0_tile_pd0_wrap_iso_en_stftile1(unsigned int utile_pd0_wrap_iso_en_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd0_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd0_wrap_mtcmos_pwr_on_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd1_wrap_iso_en_stftile1(unsigned int utile_pd1_wrap_iso_en_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd1_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd1_wrap_mtcmos_pwr_on_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd2_wrap_iso_en_stftile1(unsigned int utile_pd2_wrap_iso_en_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd2_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd2_wrap_mtcmos_pwr_on_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd3_wrap_iso_en_stftile1(unsigned int utile_pd3_wrap_iso_en_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd3_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd3_wrap_mtcmos_pwr_on_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd4_wrap_iso_en_stftile1(unsigned int utile_pd4_wrap_iso_en_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd4_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd4_wrap_mtcmos_pwr_on_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd5_wrap_iso_en_stftile1(unsigned int utile_pd5_wrap_iso_en_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_pd5_wrap_mtcmos_pwr_on_stftile1(unsigned int utile_pd5_wrap_mtcmos_pwr_on_stftile1);
int iSetSTFTILE1_POWER_CFG_0_tile_qcm_bypass_stftile1(unsigned int utile_qcm_bypass_stftile1);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm0(unsigned int usrst_req_wol_por_stftile1_qcm0);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm0(unsigned int usrst_req_wol_comb_stftile1_qcm0);
int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm0(unsigned int uwol_rst_sel_stftile1_qcm0);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm1(unsigned int usrst_req_wol_por_stftile1_qcm1);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm1(unsigned int usrst_req_wol_comb_stftile1_qcm1);
int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm1(unsigned int uwol_rst_sel_stftile1_qcm1);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm2(unsigned int usrst_req_wol_por_stftile1_qcm2);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm2(unsigned int usrst_req_wol_comb_stftile1_qcm2);
int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm2(unsigned int uwol_rst_sel_stftile1_qcm2);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm3(unsigned int usrst_req_wol_por_stftile1_qcm3);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm3(unsigned int usrst_req_wol_comb_stftile1_qcm3);
int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm3(unsigned int uwol_rst_sel_stftile1_qcm3);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm4(unsigned int usrst_req_wol_por_stftile1_qcm4);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm4(unsigned int usrst_req_wol_comb_stftile1_qcm4);
int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm4(unsigned int uwol_rst_sel_stftile1_qcm4);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_por_stftile1_qcm5(unsigned int usrst_req_wol_por_stftile1_qcm5);
int iSetSTFTILE1_POWER_CFG_1_srst_req_wol_comb_stftile1_qcm5(unsigned int usrst_req_wol_comb_stftile1_qcm5);
int iSetSTFTILE1_POWER_CFG_1_wol_rst_sel_stftile1_qcm5(unsigned int uwol_rst_sel_stftile1_qcm5);
int iSetSTFTILE1_POWER_ACK_tile_pd0_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd0_wrap_mtcmos_pwr_ack_stftile1);
int iSetSTFTILE1_POWER_ACK_tile_pd1_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd1_wrap_mtcmos_pwr_ack_stftile1);
int iSetSTFTILE1_POWER_ACK_tile_pd2_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd2_wrap_mtcmos_pwr_ack_stftile1);
int iSetSTFTILE1_POWER_ACK_tile_pd3_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd3_wrap_mtcmos_pwr_ack_stftile1);
int iSetSTFTILE1_POWER_ACK_tile_pd4_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd4_wrap_mtcmos_pwr_ack_stftile1);
int iSetSTFTILE1_POWER_ACK_tile_pd5_wrap_mtcmos_pwr_ack_stftile1(unsigned int utile_pd5_wrap_mtcmos_pwr_ack_stftile1);


#endif // SMF0_HARDEN_C_UNION_DEFINE_H
